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1 ps8924c 10/05/09 advance information - company confidential all trademarks are property of their respective owners. pi3hdmi101 1:1 active hdmi? redriver? with optimized equalization & i 2 c buffer features ? supply voltage, v dd = 3.3v 5% ? support for both dvi and hdmi tm signals ? supports both ac-coupled and dc-coupled inputs ? supports deep color tm ? high performance, up to 2.5 gbps per channel ? 5v tolerance on i 2 c path ? integrated 50-ohm (10%) termination resistors at each high speed signal input ? rx sense support, clk-off channel is switched to 250k-ohm pull-up vs. 50-ohm pull-up ? con gurable output swing control (400mv, 500mv, 600mv, 750mv, 1000mv) ? con gurable pre-emphasis levels (0db, 1.5db, 3.5db, & 6.0db, 9.0db) ? con gurable de-emphasis (0db, -3.5db, -6.0db, -9.5db) ? optimized equalization single default setting will support all cable lengths ? 8kv contact esd protection on all input/output data channels per iec 61000-4-2 ? hot insertion support on output high speed pins & scl/sda pins only ? propagation delay 1ns ? high impedance outputs when disabled ? packaging (pb-free & green): 42-contact tqfn (zh42) description pericom semiconductor?s pi3hdmi101 1:1 active redriver? circuit is targeted for high-resolution video networks that are based on dvi/hdmi tm standards and tmds signal processing. the pi3hdmi101 is an active redriver with hi-z outputs. the device receives differential signals from selected video components and drives the video display unit. this solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. each complete hdmi/dvi channel also has slower speed, side band signals, that are required to be switched. pericom?s solution provides a complete solution by integrating the side band buffer together with the high speed buffer in a single solution. using equalization at the input of each of the high speed channels, pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. the elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). the maximum dvi/hdmi bandwidth of 2.5 gbps provides 36- bit deep color? support, which is offered by hdmi revision 1.3. the pi3hdmi101 also provides enhanced robust esd/eos protection of 8kv, which is required by many consumer video networks today. the optimized equalization provides the user a single optimal setting that can provide hdmi compliance for all cable lengths: 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. pericom also offers the ability to ne tune the equalization settings in situations where cable length is known. for example, if 25meter cable length is required, pericom's solution can be adjusted to 16db eq to accept 25meter cable length. 09-0055
2 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. pin con guration tmds receiver block clk+/- 250kohm r av 1 r 2 dd control rx sense each high speed data and clock input has the same integrated equalization that can eliminate deterministic jitter caused by input traces or cables. all activity can be con t gured using pin strapping. the rx block is designed to receive all relevant signals directly from the hdmi? connector without any additional circuitry, 3 high speed tmds data, 1 pixel clock, and ddc signals. pixel clock channel has following termination scheme for rx sense support. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42414039 18192021 scl_t vdd gnd out_clkC out_clk+ vdd out_d0C out_d0+ gnd out_d1C out_d1+ vdd out_d2C out_d2+ gnd vdd oc_s3 eq_s0 eq_s1 gnd in_clkC in_clk+ vdd in_d0C in_d0+ gnd in_d1C in_d1+ vdd in_d2C in_d2+ gnd rx_sense dcc_en oe oc_s0 oc_s1 oc_s2 iadj scl_r sda_r sda_t gnd rx sense lr 2 switch is open, clk+/- termination is 250k ? hr 2 switch is closed, clk+/- termination is 50 ? although the tmds clock input channel (pin 4 and 5) has different termination scheme when port is off, user can still connect tmds data channels to these pins for better layout if required. any of the 4 differential inputs and outputs can have data or clock signals passing through. 09-0055
3 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. i 2 c buffer buffert bufferr portr portt iadj,ddc_en the vol of the buffer r is around 0.2v. the vol of the buffer t is around 0.7v. functional truth tables iadj external pull-up range h 1k to 2k (hdmi spec) l > 3k (4.7k typically) ddc_en port t / port r (if no external pull-up resistor l hi-z (i 2 c buffer disable) h(i 2 c buffer enable) 09-0055
4 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. pin description pin # pin name i/o description 5 8 11 14 in_clk+ in_d0+ in_d1+ in_d2+ i tmds positive inputs 4 7 10 13 in_clk- in_d0- in_d1- in_d2- i tmds negative inputs 3, 9, 15, 24, 30, 36 gnd p ground 18 oe i output enable, active low 41 scl_r i/o ddc clock , source side 40 sda_r i/o ddc data, source side 6, 12, 23, 27, 33, 37 v dd p 3.3v power supply 34 31 28 25 out_clk+ out_d0+ out_d1+ out_d2+ o tmds positive outputs 35 32 29 26 out_clk- out_d0- out_d1- out_d2- o tmds negative outputs 1 2 eq_s0 eq_s1 i equalizer controls, both pins with internal pull-ups 19 20 21 22 oc_s0 oc_s1 oc_s2 oc_s3 i output buffer controls note: all 4 pins have internal pull-ups 17 ddc_en i i 2 c path enable 38 scl_t i/o ddc clock, sink side 39 sda_t i/o ddc data, sink side 16 rx_sense i rx_sense control 42 iadj i high/low voltage selection, depends on i 2 c external pull-up range 09-0055
5 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. r e vi ec er qe hti w r e vi ec er qe hti w r e vi ec er qe hti w r e vi ec er qe hti w eq_s1 eq_s 0 in_d0+ in_d0- in_d1+ in_d1- in_d2+ in_d2- dd v r2 r2 250k r1 r1 150k in_clk+ in_clk- out_d0+ out_d0- out_d1+ out_d1- out_d2+ out_d2- out_clk+ out_clk- tmds drive tmds drive tmds drive tmds drive oc_s0 oc_s1 oc_s2 oc_s3 oe control buffer t buffer r port r port t iadj, ddc_en dd v dd v dd v 50 50 50 50 50 50 complete high speed input rx block is as follows: 09-0055
6 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. truth table oe function 0 active 1 all tmds outputs are hi-z eq setting value logic table eq_s1 (2) eq_s0 (2) setting value @ 825mhz 0 0 3db on all high speed inputs 0 1 8db on all high speed inputs 1 0 12db on all high speed inputs 1 1 16db on all high speed inputs notes: 1. external pull-ups are required along scl/sda path 2. internal 100kohm pull-ups truth table 1 oc_s3 (2) oc_s2 (2) oc_s1 (2) oc_s0 (2) vswing (mv) pre/de-emphasis 0000500 0 0001600 0 0010750 0 00111000 0 0100500 0 0101500 1.5db 0110500 3.5db 0111500 6db 1000400 0 1001400 3.5db 1010400 6db 1011400 9db 11001000 0 1101660 -3.5db 1110500 -6db 1111330 -9db 09-0055
7 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. storage temperature .................................................... ?65c to +150c supply voltage to ground potential ................................ ?0.5v to +4.0v dc input voltage ...............................................................?0.5v to v dd dc output current ....................................................................... 120ma power dissipation ........................................................................... 1.0w note: stresses greater than those listed under max i mum rat ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. exposure to ab- solute max i mum rating con di tions for extended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) recommended operating conditions symbol parameter min. typ. max. units v dd supply voltage 3.135 3.3 3.465 v t a operating free-air temperature 0 70 c tmds differential pins v id receiver peak-to-peak differential input voltage 150 1560 mvp-p v ic input common mode voltage 2 v dd + 0.01 v v dd tmds output termination voltage 3.135 3.3 3.465 r t termination resistance when rxsense pin is high 45 50 55 ohm tmds data rate signaling rate 0.25 2.5 gbps control pins (oc_sx, eq_sx, oe, ddc_en) v ih lvttl high-level input voltage 2 v dd v v il lvttl low-level input voltage gnd 0.8 ddc pins (scl_r, scl_t, sda_r, sda_t) v i(ddc) input voltage gnd 5.5 v i 2 c pins (scl_t, sda_t) v ih high-level input voltage 0.7 x v dd 5.5 v v il low-level input voltage -0.5 0.3 x v dd v icl low-level input voltage contention (1) -0.5 0.4 i 2 c pins (scl_r, sda_r) v ih high-level input voltage 0.7 x v dd 5.5 v v il low-level input voltage -0.5 0.3 x v dd note: 1. vil speci cation is for the rst low level seen by the scl/sda lines. v icl is for the second and subsequent low levels seen by the tscl/tsda lines. 09-0055
8 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. symbol parameter test conditions min. typ. (1) max. units i dd supply current v ih = v dd , v il = v dd - 0.4v, r t = 50-ohm, v dd = 3.3v data inputs = 1.65 gbps hdmi data pattern clk inputs = 165 mhz clock oc_sx = low, x = 0,1,2,3 120 ma p d power dissipation 400 mw i ddq standby current oe = high, vdd = 3.3v, source = off 2ma tmds differential pins v oh single-ended high-level output voltage v dd = 3.3v, r t = 50-ohm pre-emphasis/de-emphasis = 0db v dd - 10 v dd + 10 mv v ol single-ended low-level output voltage v dd - 600 v dd - 400 v swing single-ended output swing voltage 400 600 v od(o) overshoot of output differential voltage 6% 15% 2x v swing v od(u) undershoot of output differential voltage 12% 25% v oc(ss) change in steady-state common-mode output voltage between logic states 0.5 5 mv i (os) short circuit output current 12 ma v ode(ss) steady state output differential voltage oc_sx = gnd, data inputs = 250 mbps hdmi data pattern, 25 mhz pixel clock, x = 0,1,2,3 560 840 mvp-p v ode(pp) peak-to-peak output differential voltage 800 1200 v i(open) single-ended input voltage under high impedance input or open input i i = 10a v dd - 10 v dd + 10 mv r int input termination resistance v in = 2.9v, rxsense pin = high 45 50 55 ohm control pins (oe, ddc_en, iadj) i ih high-level digital input current v ih = 2v or v dd -10 10 a i il low-level digital input current v i = gnd or 0.8 v -10 10 i 2 c pins (scl_t, sda_t) (t port) i ikg input leakage current v i = 5.5 v -50 50 a v i = v dd -20 20 i oh high-level output current v o = 3.6 v -10 10 i il low-level input current v il = gnd -40 40 v ol low-level output voltage i ol = 2.5 ma iadj = h 0.65 0.9 v c io 1 input/output capacitance v dd = 0v or 3.0v, frequency = 100khz 47pf v oh(ttl) 2 ttl high-level output voltage i oh = -8 ma 2.4 v v ol(ttl) 2 ttl low-level output voltage i ol = 8 ma 0.4 note: 1. measured at vbias = 0v or 5v, vrms = 0.2v; vbias = 1.65v, vrms = 0.84v; vbias = 2.5v, vrms = 1.2v. 2. voh/vol of external driver at the r and t ports. (table continued) electrical characteristics (over recommended operating conditions unless otherwise noted) 09-0055
9 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. switching characteristics (over recommended operating conditions unless otherwise noted) symbol parameter test conditions min. typ. (1) max. units tmds differential pins tpd propagation delay v dd = 3.3v, r t = 50-ohm, pre-emphasis/de-emphasis = 0db 2000 ps t r differential output signal rise time (20% - 80%) 75 240 t f differential output signal fall time (20% - 80%) 75 240 t sk(p) pulse skew 10 50 t sk(d) intra-pair differential skew 23 50 t sk(o) inter-pair differential skew (2) 100 t clkjit(pp) peak-to-peak output jitter for tmds clock channel pre-emphasis/de-emphasis = 0db, data inputs = 1.65 gbps hdmi data pattern clk input = 165 mhz clock 15 30 t data jit(pp) peak-to-peak output jitter for tmds data channels 18 50 t de de-emphasis duration de-emphasis = -3.5db, data inputs = 250 mbps hdmi data pattern, clk output = 25 mhz clock 240 t sx select to switch output 10 ns t en enable time 200 t dis disable time 10 i 2 c pins (scl_r, sda_r, scl_t, sda_t) t plh propagation delay time, low-to-high-level output scl_t/sda_t to scl_r/sda_r iadj = v dd c load = 300 pf tbuffer : rpu = 2k, vpu = 3.0v 500 ns t phl propagation delay time, high-to-low-level output scl_t/sda_t to scl_r/sda_r 136 t plh propagation delay time, low-to-high-level output scl_t/sda_t to scl_r/sda_r rbuffer : rpu = 1.2k, vpu = 3.3v or rpu = 1.8k, vpu = 5v iadj = gnd c load = 100 pf 450 t phl propagation delay time, high-to-low-level output scl_t/sda_t to scl_r/sda_r 136 t r scl_t/sda_t output signal rise time see fig. a 999 t f scl_t/sda_t output signal fall time 90 t r scl_r/sda_r output signal rise time 999 t f scl_r/sda_r output signal fall time 90 t set enable to start condition 6 10 t hold enable after stop condition 6 10 i 2 c pins (scl_r, sda_r port) i ikg input leakage current v i = 5.5 v -50 50 a v i = v dd -10 10 i oh high-level output current v o = 3.6 v -10 10 i il low-level input current v il = gnd -10 10 v ol low-level output voltage i ol = 4 ma, iadj = h 0.2 v c i input capacitance v i = 5.0 v or 0 v, freq = 100khz 25 pf v i = 3.0 v or 0 v, freq = 100khz 10 09-0055
10 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. pulse generator d.u.t. v dd 3.3v10% r=1.2k l c=100pf l v in v iout pulse generator d.u.t. v dd 3.3v10% r=2k l c=300pf l v in v iout iadj=l iadj=h t f t f 20% 80% 20% 80% t phl t plh rscl/rsda input tscl/tsda input v dd v dd /2 0.1v 3.3v10% 1.5v v ol t f t f 20% 80% 20% 80% t phl t plh rscl/rsda input tscl/tsda input v dd 1.5v 0.1v 5v10% v ol v dd /2 t plh figure a. i 2 c timing test circuit and de nition 09-0055
11 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. tmds output oscillation elimination the tmds inputs do not incorporate a squelch circuit. therefore, we recommend the input to be externally biased to prevent output oscillation. one pin will be pulled high to v dd with the other grounded through a 1.5k-ohm resistor as shown. tmds input fail-safe recommendation s s s s r t r t av cc v dd tmds tmds driver receiver r int r int 1.5kohm 09-0055
12 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. recommended power supply decoupling circuit figure 1 is the recommended power supply decoupling circuit con guration. it is recommended to put 0.1 f decoupling capacitors on each v dd pins of our part, there are four 0.1 f decoupling capacitors are put in figure 1 with an assumption of only four v dd pins on our part, if there is more or less v dd pins on our pericom parts, the number of 0.1 f decoupling capacitors should be adjust- ed according to the actual number of v dd pins. on top of 0.1 f decoupling capacitors on each v dd pins, it is recommended to put a 10 f decoupling capacitor near our part?s v dd , it is for stabilizing the power supply for our part. ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. but, it is optional and depends on the power supply conditions of other circuits. figure 1 recommended power supply decoupling circuit diagram pericom part vdd vdd vdd vdd from main power supply 0.1f 0.1f 0.1f 0.1f ferrite bead 10f 09-0055
13 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. requirements on the decoupling capacitors there is no special requirement on the material of the capacitors. ceramic capacitors are generally being used with typically materi- als of x5r or x7r. layout and decoupling capacitorplacement consideration i. each 0.1 f decoupling capacitor should be placed as close as possible to each v dd pin. ii. v dd and gnd planes should be used to provide a low impedance path for power and ground. iii. via holes should be placed to connect to v dd and gnd planes directly. iv. trace should be as wide as possible v. trace should be as short as possible. vi. the placement of decoupling capacitor and the way of routing trace should consider the power owing criteria. vii. 10f capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 f capacitors. viii. avoid the large current circuit placed close to our part; especially when it is shared the same v dd and gnd planes. since large current owing on our v dd or gnd planes will generate a potential variation on the v dd or gnd of our part. figure 2 layout and decoupling capacitor placement diagram pericom part gnd plane v dd plane 0.1uf bypass noise power flow 09-0055
14 ps8924c 10/05/09 pi3hdmi101 1:1 active hdmi tm redriver with optimized equalization & i 2 c buffer advance information - company confidential all trademarks are property of their respective owners. pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com ordering information ordering code package code package description pi3hdmi101zhe zh 42-pin, pb-free & green tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? adding an x suf x = tape/reel package mechanical: 42-pin, low pro le quad flat package (zh42) description: 42-contact thin fine pitch quad flat no-lead (tqfn) package code: zh (zh42) document control #: pd-2035 revision: c date: 02/17/09 notes: 1. all dimensions are in millimeters, angles in degrees. 2. coplanarity applies to the exposed thermal pad as well as the terminals. 3. refer jedec mo-220 4. recommended land pattern is for reference only. 5. thermal pad soldering area 09-0116 application information supply voltage all v dd pins are recommended to have a 0.01 f capacitor tied from v dd to gnd to lter supply noise tmds inputs standard tmds terminations have already been integrated into pericom?s pi3hdm101 device. therefore, external terminations are not required. any unused port must be left oating and not tied to gnd. note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 09-0055

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